Analog Design Engineer with High-speed Io Design

We are seeking a Senior Analog Design Engineer with deep expertise in High‑Speed I/O (HSIO) and SerDes design to help build next‑generation analog and mixed‑signal IPs. In this high‑impact role, you will take ownership of architecture, circuit design, simulations, verification, and silicon bring‑up for multi‑Gbps interfaces on advanced technology nodes.

You will work on complex, performance‑driven designs and influence key architectural decisions. The role provides strong technical visibility, hands‑on design challenges, and the opportunity to collaborate with experienced teams across digital, physical design, packaging, and systems engineering. You will also mentor junior engineers and contribute to shaping design methodologies and best practices.

Key Responsibilities

• Hands-on design experience in High-Speed I/O (HSIO) and SerDes PHY including PLLs, CDRs, equalizers, and multi‑Gbps analog blocks.
• Design and optimization of analog/mixed-signal circuits for high‑speed I/O interfaces:
• TX/RX front-ends
• PLL, DLL, CDR architectures
• CTLE, DFE, FFE equalization
• Biasing, termination, ESD-aware structures
• Lead block‑level architecture and circuit design for I/O subsystems.
• Perform detailed transistor-level simulations (AC, transient, noise, jitter, BER).
• Drive pre‑layout and post‑layout verification (including parasitic extraction).
• Analyze and mitigate SI challenges (channel loss, crosstalk, reflections).
• Support layout floorplanning; ensure analog‑performance‑aware routing.
• Collaborate with digital, physical design, packaging & system teams.
• Participate in silicon bring‑up, lab characterization & debug.
• Ensure compliance with interface specifications and PVT robustness.
• Mentor junior engineers and contribute to design reviews.

Required Qualifications

• Proven experience designing high‑speed I/O circuits in CMOS.
• Strong understanding of: Jitter, noise, BER, eye diagrams
• Signal integrity & channel modeling
• Proficient with SPICE simulators (Spectre, HSPICE, Eldo).
• Solid understanding of CMOS device physics and PVT variations.
• Experience working on advanced/scaled technology nodes.
• Ability to independently own and drive design blocks.