Design Verification Engineer

Title: Sr. Design Verification Engineer

Type: Contract

Duration: up to 12 months (maybe longer)

Location: Remote

We are seeking a highly skilled Senior ASIC Design Verification Engineer to lead and execute verification of high-performance UCIe (Universal Chiplet Interconnect Express) IP and advanced SoC subsystems. This role focuses on developing scalable, coverage-driven verification environments for next-generation chiplet-based architectures used in AI, HPC, networking, and automotive applications.

You will work closely with architecture, design, and physical implementation teams to ensure functional correctness, protocol compliance, and high-quality silicon delivery.

Key Responsibilities

• Lead functional verification of UCIe IP and subsystems from specification through silicon validation.
• Develop and maintain SystemVerilog / UVM-based verification environments.
• Create reusable verification components, agents, scoreboards, and checkers.
• Define and execute verification plans, including coverage models and regression strategies.
• Implement protocol compliance checking for UCIe, PCIe, CXL, and related interfaces.
• Perform constrained-random, directed, and stress testing.
• Drive functional coverage closure and bug triage.
• Collaborate with RTL designers to debug and resolve functional issues.
• Integrate third-party IP into verification environments.
• Support emulation, FPGA prototyping, and post-silicon validation efforts when required.
• Mentor junior verification engineers and contribute to best practices.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of hands-on ASIC/SoC Design Verification experience.
• Strong expertise in SystemVerilog and UVM.
• Proven experience verifying high-speed interconnect or protocol IP.
• Solid understanding of:
• UCIe architecture and protocol layers
• Link training and state machines
• Flow control and error handling
• Power management and reset sequences
• Experience with industry simulators (Questa, VCS, Xcelium, etc.).
• Strong debugging skills using waveform and log analysis tools.
• Experience with functional and code coverage tools.

Preferred Qualifications

• Direct experience verifying UCIe IP in production silicon.
• Knowledge of related protocols: PCIe, CXL, AXI, CHI.
• Experience with portable stimulus (PSS) methodologies.
• Familiarity with formal verification techniques.
• Exposure to emulation platforms and FPGA prototyping.
• Experience with multi-die/chiplet architectures.
• Scripting skills (Python, Perl, TCL, Bash).
• Prior experience in leading verification projects.