Fpga Design/verification Engineer with Security Clearance

Position: FPGA Design Engineer
Location: Sunnyvale, CA
Rolling Contract
Secret Clearance Required Responsible for ASIC and FPGA verification on R&D programs; serves as a UVM verification expert Verifies FPGA and/or ASIC designs, including creation of UVM verification environments, testbenches, tests, and coverage models Develops and improves automation and verification scripts to enhance FPGA verification efficiency and reduce cost Collaborates cross-functionally with RTL designers, systems architects, RF/analog and digital circuit designers, and ASIC/FPGA engineers to deliver next-generation, high-speed networking products Contributes to simulation, verification, integration, and test of complex, high-speed systems Provides technical guidance and support to junior engineers.