Senior Design Verification Engineers_eximietas Design

🚀 We’re Hiring – Senior Design Verification (PCIe) Professionals.

📅 Apr 2026 Hiring

Greetings from Eximietas Design!

We are looking for highly experienced SoC Design Verification professionals (PCIe focus) to join our growing global team.

🔎 Experience Required:

Min 5 to 20+ Years

Locations:

• India:

Bengaluru, Hyderabad, Pune & Ahmedabad.

USA Eligibility:

• USA: San Jose (Bay Area) / Austin
• U.S. Permanent Residents (Green Card holders) only

💼 Key Responsibilities:

• Lead SoC Design Verification for complex projects
• Develop verification strategies, test plans, testbenches & coverage models
• Verify high-speed & low-speed protocols:
• I2C / I3C, SPI, UART, GPIO, QSPI
• PCIe, Ethernet, CXL, MIPI, DDR, HBM
• Perform Gate-level simulations & power-aware verification (Xprop, UPF)
• Implement SystemVerilog assertions & functional coverage
• Work closely with architects, RTL, and pre/post-silicon teams
• Ensure verification signoff with proper documentation
• Mentor junior engineers & lead verification teams
• Integrate third-party VIPs (Synopsys / Cadence)

🔧 Technical Expertise Required:

• 5+ years of hands-on SoC Design Verification experience
• Strong SystemVerilog (Assertions & Coverage) skills
• Experience with VCS (Synopsys) & Xcelium/Xsim (Cadence)
• High-speed SoC protocol verification expertise
• Experience in power-aware verification using UPF
• Strong collaboration & leadership skills

⭐ Preferred:

• Third-party VIP integration experience
• Experience leading large DV teams
• Pre-silicon & Post-silicon exposure

📩 Interested engineers can share resumes at: maruthiprasad.e@eximietas.design

🤝 Referrals are highly appreciated — please share within your network!

Best Regards,

Maruthy Prasaad

Associate VLSI Manager – Talent Acquisition | Visakhapatnam

Eximietas Design

📧 maruthiprasad.e@eximietas.design

📱 +91 8088969910